A novel approach for reducing the area occupied by contact pads on process control chips

Author

Walton, A.J. ; Gammie, W. ; Morrow, D. ; Stevenson, J.T.M. ; Holwill, R.J.

Author_Institution

Dept. of Electr. Eng., Edinburgh Univ., UK

fYear

1990

fDate

5-7 March 1990

Firstpage

75

Lastpage

80

Abstract

An approach which reduces the number of pads required by electrical test structures is presented. The multiplexed scheme requires only two levels of interconnect and enables more devices to be located in a given area, providing the designer of test structures with more freedom to experiment with structures previously requiring a large number of pads. Applications for transistors, electrical verniers, yield monitoring, reliability evaluations, continuity tests, and measuring the resistance of tracks are discussed.<>

Keywords

integrated circuit technology; integrated circuit testing; multiplexing; contact pad area reduction; contact pad number reduction; continuity tests; electrical test structures; electrical verniers; microelectronic test chips; multiplexed interconnect scheme; multiplexed scheme; process control chips; reliability evaluations; track resistance measurement; transistors; two levels of interconnect; yield monitoring; Ammeters; Atherosclerosis; Contacts; Electric variables measurement; Electrical resistance measurement; Force measurement; Integrated circuit interconnections; Process control; Resistors; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on

Conference_Location

San Diego, CA, USA

Type

conf

DOI

10.1109/ICMTS.1990.67883

Filename

67883