Title :
Autonomous fault masking processor
Author_Institution :
Dept. of Inf. & Comput. Sci., Toyo Univ., Kawagoe, Japan
Abstract :
The author describes the architecture of fault tolerant processors. It features fault masking by majority voting, based on the cell´s reliability. Each node cell must consist of two operation modes; one is its own native operation mode while the other is the subject cell´s copied operation mode, where the cell reliability can be assessed by self-recognition. Two possible implementations for array and tree structures are presented, and simulations for the fault-tolerant effectiveness of these architectures are given.<>
Keywords :
fault tolerant computing; parallel processing; autonomous fault masking processor; cell reliability; fault tolerant processors; majority voting; operation mode; simulations; tree structures; Computational modeling; Computer architecture; Fault tolerance; Manufacturing processes; Parallel processing; Pipeline processing; Redundancy; Timing; Tree data structures; Voting;
Conference_Titel :
Compcon Spring '93, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-3400-6
DOI :
10.1109/CMPCON.1993.289675
