XDBus: a high-performance, consistent, packet-switched VLSI bus

Author

Sindhu, P. ; Frailong, J.-M. ; Gastinel, J. ; Cekleov, M. ; Yuan, L. ; Gunning, B. ; Curry, D.

Author_Institution

Xerox Palo Alto Res. Center, CA, USA

fYear

1993

fDate

22-26 Feb. 1993

Firstpage

338

Lastpage

344

Abstract

The XDBus is a low-cost, synchronous, packet-switched VLSI bus designed for use in high-performance multiprocessors. The bus provides an efficient coherency protocol which guarantees processors a consistent view of memory in the presence of caches and IO. Low-voltage swing (GTL) CMOS drivers connected to balanced transmission line traces ensure low power as well as high speed for chip, board, and as backplane applications. The signaling scheme and coherency protocol work together to promote a high level of system integration, while permitting a wide variety of configurations to be realized. These configurations include small single board systems, multiple bus systems, multiboard backplane systems, and multilevel cache systems. The bus is used in several commercial systems including Sun Microsystem´s new SPARCcenter 2000 series.<>

Keywords

VLSI; multiprocessing systems; packet switching; protocols; system buses; SPARCcenter 2000 series; XDBus; backplane applications; balanced transmission line traces; caches; coherency protocol; high-performance multiprocessors; low voltage swing CMOS drivers; packet-switched VLSI bus; Backplanes; Bandwidth; CMOS technology; Costs; Low voltage; Packaging; Power system interconnection; Protocols; Sun; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '93, Digest of Papers.

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-3400-6

Type

conf

DOI

10.1109/CMPCON.1993.289691

Filename

289691