Title :
Generic ASIC architecture for digital signal processing
Author :
Smith, Stewart G. ; Morgan, Ralph W. ; Payne, Julian G.
Author_Institution :
VLSI Technol., Valbonne, France
Abstract :
The architectural methodology behind a novel high-level VLSI cell compiler currently under development is described. The tool is aimed specifically at digital signal processing applications, synthesizing powerful arithmetic kernel processors from high-level parameterized schematics. Underlying the tool is a generic pipelined numerical processing architecture, flexible enough in its use of innate parallelism to meet a wide range of throughput requirements with minimal waste of resources. Machines are synthesized using this architecture as a blueprint. To this end, the tool encapsulates the essential knowledge required to assemble a useful set of arithmetic operators over all local and global parametric combinations. Some multiplier instances are illustrated
Keywords :
application specific integrated circuits; digital arithmetic; digital signal processing chips; parallel architectures; pipeline processing; architectural methodology; arithmetic kernel processors; arithmetic operators; digital signal processing; generic pipelined numerical processing architecture; global parametric combinations; high-level VLSI cell compiler; high-level parameterized schematics; innate parallelism; throughput requirements; Application specific integrated circuits; Arithmetic; Digital signal processing; Integrated circuit technology; Parallel processing; Pipeline processing; Signal synthesis; Space technology; Throughput; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63333
