Title :
Managing and controlling contamination in an advanced 8" CMOS pilot line
Author :
De Backker, K. ; Deweerd, W. ; Lebon, H.
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
In this paper we will elaborate on experience that has been built up at IMECs class 1 R&D fab, based on a scheme for contamination control that allows to safely and simultaneously introduce a multitude of contaminants in a single tool park and requiring only limited means of contamination dedicated tool allocation. Emphasis will be put on Cu/low k related research. Details will be given on various aspects, ranging from the employed specs, operational strategy and allocation, over classification schemes for various contaminants, to long-term monitoring
Keywords :
CMOS integrated circuits; integrated circuit technology; surface contamination; 8 in; CMOS pilot line; Cu; Cu/low-k processing; contamination control; semiconductor fab; tool allocation; Conducting materials; Contamination; Costs; Dielectric materials; Hazardous materials; Hazards; Manufacturing processes; Production; Research and development; Research and development management;
Conference_Titel :
Semiconductor Manufacturing Symposium, 2001 IEEE International
Conference_Location :
San Jose, CA
Print_ISBN :
0-7803-6731-6
DOI :
10.1109/ISSM.2001.963006
