Title :
Xtmap: generate-and-test mapper for table-lookup gate arrays
Author_Institution :
California Univ., Santa Cruz, CA, USA
Abstract :
Introduces Xtmap, a technology mapper for f-input table-lookup cells based on a generate-and-test paradigm. Xtmap can optimize for area and delay simultaneously and produces smaller circuits than previous mappers that considered delay, while matching their delay values. Tables of benchmark results are used to compare Xtmap with Xmap, Dagmap, FlowMap, chortle-d, and mis-pga covering algorithms.<>
Keywords :
delays; logic CAD; logic arrays; logic testing; optimisation; table lookup; Dagmap; FPGA; FlowMap; Xilinx; Xmap; Xtmap; area optimization; benchmark results; chortle-d; combinational logic synthesis; covering algorithms; delay optimization; f-input table-lookup cells; gate arrays; generate-and-test mapper; mis-pga; technology mapper; technology mapping; Circuit testing; Delay; Dynamic programming; Field programmable gate arrays; Greedy algorithms; Law; Legal factors; Libraries; Logic; Minimization;
Conference_Titel :
Compcon Spring '93, Digest of Papers.
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-3400-6
DOI :
10.1109/CMPCON.1993.289703
