A crossbridge for measurement of gate-limited source/drain diffusion

For self-aligned CMOS technology a test structure for measuring and controlling the electrical width of the source-drain diffusion, the gate-limited source drain crossbridge, and supporting electrical data is described. The results of the linewidth measurements are shown. The distribution of the difference between the polysilicon line spacing and the source-drain diffusion width is shown. A variation in source-drain diffusion width which is larger than the experimental error and not attributable only to the variation in polysilicon linewidth is detected. Additional factors which contribute to source-drain dimension variations are described.<>