Title :
Design and optimization of SCR devices for on-chip ESD protection in advanced SOI CMOS technologies
Author :
Li, Junjun ; Sarro, James Di ; Gauthier, Robert
Author_Institution :
Semicond. R&D Center, IBM, Essex Junction, VT, USA
Abstract :
We present design and optimization results of ESD SCR devices in advanced SOI CMOS technologies. Anode to cathode spacing, body resistance and Diode string or RC trigger circuits affect SCR turn-on characteristics. 100ns TLP failure current up to 10.1mA/um and record transient turn-on time down to ~75ps with a leakage current of ~10nA are demonstrated.
Keywords :
CMOS integrated circuits; anodes; cathodes; circuit optimisation; electrostatic discharge; failure analysis; silicon-on-insulator; thyristors; trigger circuits; ESD SCR device optimisation; RC trigger circuits; SCR turn-on characteristics; TLP failure; advanced SOI CMOS technology; anode spacing; body resistance; cathode spacing; diode string; on-chip ESD protection; time 100 ns; transmission line pulser; Anodes; CMOS integrated circuits; CMOS technology; Capacitance; Electrostatic discharges; Fingers; Thyristors;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2012 34th
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-4673-1467-1
