Abstract :
A partitioning-based placement algorithm with priori wirelength estimation called HJ-hPl is presented in this paper. We propose a new methodology to estimate proximity of wirelengths in a netlist, which is capable of estimating not only short interconnects but long interconnects accurately. We embed the wirelength estimation into the partitioning tool of our global placement, which can guide our placement towards a solution with shorter wirelengths. In addition, we employ a regular structure clustering technique to reduce the size of the original placement, which can also bring on a tighter placement result. Experimental results show that, compared to Capo10.5, mPL6, and NTU place, HJ-hPl outperforms theirs in term of wirelength and run time. The improvements in terms of average wirelength over Capo10.5, mPL6 and NPUplace are 13%, 3%, and 9%with only 19%, 91%, and 99% of their runtime,respectively. By integrating our estimated wirelength driven clustering into Capo10.5, we are able to reduce average wirelength by 3%.
Keywords :
VLSI; integrated circuit design; hierarchical mixed-size placement algorithm; partitioning tool; priori wirelength estimation; structure clustering technique; Algorithm design and analysis; Application specific integrated circuits; Clustering algorithms; Design automation; Design engineering; Integrated circuit interconnections; Iterative algorithms; Partitioning algorithms; Runtime; Very large scale integration; VLSI; mixed-size; partitioning; placement; wirelength estimation;