Title :
CubeCuts: A Novel Cutting Scheme for Packet Classification
Author :
Chang, Yeim-Kuan ; Wang, Yu-Hsiang
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
Packet Classification is one of the most important services provided by Internet routers nowadays. Decision-tree based schemes, such as HiCuts and HyperCuts, are the most well-known algorithms. These schemes separate search space into many equal-sized sub-spaces. But both schemes have the same rule replication problem, which might cause large memory overhead. Although another decision-tree based solution, Hyper splits, was proposed to cut space according to end-points for reducing the memory requirement, we still observe that its rule replication problem doesn´t be solved well and the memory requirement can still be improved. In this paper, we propose a scheme called Cube Cuts to build a binary decision tree that does not generate any duplicated rule. By using the hybrid scheme that combines the Cube Cuts and constrained HiCuts, we can have a memory-efficient data structure such that the entire rule table of up to10K rules can be fit into the on-chip memory of FPGA device. Our design is very suitable to be implemented with parallelism and pipeline. The experimental results show that the rule replication ratio is very low in all rule tables (ACL, FW, and IPC). The proposed parallel and pipelined architecture based on the hybrid scheme can achieve a throughput of 118 Gbps, which is enough to deal with the Internet traffic that is growing rapidly in recent years.
Keywords :
Internet; decision trees; field programmable gate arrays; parallel architectures; pattern classification; telecommunication network routing; telecommunication traffic; FPGA device; Internet router; Internet traffic; binary decision tree; cubecuts; cutting scheme; decision-tree based scheme; decision-tree based solution; hicuts; hypercuts; memory requirement reduction; memory-efficient data structure; on-chip memory; packet classification; parallel architecture; pipelined architecture; rule replication problem; search space; Classification algorithms; Decision trees; Field programmable gate arrays; Hardware; Logic gates; Memory management; Pipelines; FPGA; decision-tree based algorithms; packet classification; pipeline;
Conference_Titel :
Advanced Information Networking and Applications Workshops (WAINA), 2012 26th International Conference on
Conference_Location :
Fukuoka
Print_ISBN :
978-1-4673-0867-0
DOI :
10.1109/WAINA.2012.110