Requirements for Stable DC Biasing of High Gain Discrete Phemts During Wafer Level Screening

DC testing of unmatched dscrete PHEMT device wafers is complicated by the tendency of such devices to oscillate under DC bias due to their iugh gain and broad frequency range. For t h ~ sre ason, dscrete PHEW wafer level screening is often limited to a small set of parameters wluch can be measured without oscillation problems. such as pinch-off voltages. drain leakage currents, and drain breakdown voltages. The typical approach to eliminating such oscillations is empirical modification of probe impedances with chp components and test station cabling. In general, such approaches are unsuccessful. This paper presents a more rigorous approach to tlus problem. Analysis of PHEMT deice characteristics is used to define the device termination impedance requirements for stable device biasing. The wafer DC test setup is configured to acheve these impedance requirements at the evice "terminals" while also maintaining necessaq Kellin and sense connections to the PHEMT\´ die from the DC test equipment.