Title :
Low-power 6-bit 1-GS/s two-channel pipeline ADC with open-loop amplification using amplifiers with local-feedback
Author :
Galhardo, A. ; Goes, J. ; Paulino, N.
Author_Institution :
Inst. Super. de Eng. de Lisboa Lisboa, Lisbon
Abstract :
A low-power 1.2 V 6-bit 1-GS/s time-interleaved pipeline ADC designed in 130 nm CMOS is described. It is based on a new 2-channel 1.5-bit MDAC that performs open-loop residue amplification using a shared amplifier employing local-feedback. Time mismatches between channels are highly attenuated, simply by using two passive front-end sample-and-hold circuits, with dedicated switch-linearization control circuits, driven by a single clock phase. Simulated results of the ADC achieve 5.35-bit ENOB, with 20 mW and without requiring any gain control/calibration scheme.
Keywords :
CMOS integrated circuits; analogue-digital conversion; passive networks; sample and hold circuits; CMOS; MDAC; open-loop residue amplification; passive front-end sample-and-hold circuits; power 20 mW; switch-linearization control circuits; time mismatches; time-interleaved pipeline ADC; two-channel pipeline ADC; voltage 1.2 V; CMOS technology; Circuit simulation; Clocks; Gain control; Logic; Pipelines; Power amplifiers; Sampling methods; Switching circuits; Timing;
Conference_Titel :
Circuits and Systems, 2008. ISCAS 2008. IEEE International Symposium on
Conference_Location :
Seattle, WA
Print_ISBN :
978-1-4244-1683-7
Electronic_ISBN :
978-1-4244-1684-4
DOI :
10.1109/ISCAS.2008.4541903
