A gain-enhancing technique for very low-voltage amplifiers

In this paper we present a gain enhancement technique for very low-voltage deep sub-micron amplifiers based on the use of a CCH-based negative impedance converter. Relaxed specifications on the current conveyor allow an easy implementation of this technique in a sub-1 V environment, where common topologies such as the cascode and the differential pair cannot be used. An example implementation in a 65-nm CMOS technology, using plusmn0.35 V supply voltage and a simple 6-transistor CCH topology, shows a 15.5-dB gain enhancement with a good robustness against process variations.