DocumentCode
1841522
Title
Buffered tree refinement considering timing and congestion
Author
Ye, Wei-Zhi ; Wang, Ting-Chi
Author_Institution
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2005
fDate
27-29 April 2005
Firstpage
63
Lastpage
66
Abstract
In this paper, we present an algorithm to improve the congestion cost and even the timing of a given buffered tree. By decomposing a buffered tree into several components and selecting alternative positions to move the drivers of these components, we can use pre-computed look-up tables to reconstruct the buffered tree such that the congestion cost and even the timing can be improved, in our experiments, we used the buffered trees which were created by S. Dechu et al. (2004) as the testcases, and the results show that our algorithm can improve the congestion cost up to 34% and the timing up to 15.8%.
Keywords
buffer circuits; network routing; table lookup; tree searching; buffered tree refinement; congestion cost; look-up tables; timing improvements; Circuit testing; Computer science; Costs; Delay; Modems; Routing; Timing; Tree graphs; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on
Print_ISBN
0-7803-9060-1
Type
conf
DOI
10.1109/VDAT.2005.1500021
Filename
1500021
Link To Document