A 1.6-GHz delta-sigma modulated fractional-N frequency synthesizer

Author

Yang, Ching-Yuan ; Jiang, Kuei-Zu ; Chen, Jen-Wen

Author_Institution

Dept. of Electr. Eng., National Chung-Hsing Univ., Taichung, Taiwan

fYear

2005

fDate

27-29 April 2005

Firstpage

157

Lastpage

160

Abstract

The goal of this work is to design a high speed, low power consumption, and low noise RF frequency synthesizer. It can be applied to the RF front-end architecture of the IEEE 802.11 b/g channels. In this work, the VCO is an LC-tank oscillator to get the low noise performance, and an all digital delta-sigma modulator, which controls the divider of the synthesizer, is designed to present the channel selection and the fractional division ratio. Basing on the theory of phase-locked loop, the concepts, several different architectures, and the implementation of the fractional-N frequency synthesizer are given. The fractional-N frequency synthesizer is fabricated in a 1.8V, 0.18μm CMOS technology, and consumes 29.05 mW in the operating frequency of 1.6 GHz.

Keywords

CMOS integrated circuits; UHF oscillators; delta-sigma modulation; frequency synthesizers; low-power electronics; phase locked loops; voltage-controlled oscillators; 0.18 micron; 1.6 GHz; 1.8 V; 29.05 mW; CMOS technology; IEEE 802.11 b/g channels; LC-tank oscillator; RF frequency synthesizer; RF front-end architecture; VCO; channel selection; digital delta-sigma modulation; fractional division ratio; fractional-N frequency synthesizer; low power consumption; phase-locked loop; 1f noise; CMOS technology; Delta modulation; Delta-sigma modulation; Energy consumption; Frequency modulation; Frequency synthesizers; Radio frequency; Signal to noise ratio; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on

Print_ISBN

0-7803-9060-1

Type

conf

DOI

10.1109/VDAT.2005.1500044

Filename

1500044