A fully digital ADC using a new delay element with enhanced linearity

Fully digital analog to digital converters (FD-ADC) have potential applications in very low power ICs and can be implemented in digital CMOS technology. In this paper the non- linearity of the delay element (DE), which is the main building block in an FD-ADC, is discussed and its impact on the overall performance of the ADC is addressed. It is shown that the non- linearity of the delay element should be within certain limits in order to achieve the best signal to noise plus distortion ratio (SNDR). Also, a new current starved delay element with enhanced linearity is proposed. Using the proposed DE, the SNDR of a 6-bit FD-ADC is improved by 7dB.