An improved methodology for system-level point-to-point communication architecture synthesis in SOC design

In this paper, we present a simple yet effective technique to improve an existing methodology for system-level point-to-point communication architecture synthesis in SOC design. The technique enables the existing methodology to simultaneously consider the chip area, communication energy, and wirelength to evaluate a candidate communication architecture under performance constraints. The improved methodology has been tested on two cases and the experimental results indicate that the average wirelength and communication energy could be reduced by up to 20.4% and 4%, respectively while the average chip area increases at most 3.1%.