DocumentCode :
1842441
Title :
Low-power test pattern generator design for BIST via non-uniform cellular automata
Author :
Kiliç, Hürevren ; Oktem, Levent
Author_Institution :
Comput. Eng. Dept., Atilim Univ., Ankara, Turkey
fYear :
2005
fDate :
27-29 April 2005
Firstpage :
212
Lastpage :
215
Abstract :
An efficient low-power test pattern generator (TPG) design for built-in self-test (BIST) is introduced. The approach uses the non-uniform cellular automata (NUCA) model. For our purpose, we designed a polynomial-time algorithm that converts the test pattern generation problem into the classical combinatorial problem called minimum set covering (MSC) which is known to be NP-complete. Solutions to the MSC problems give the low-power design topology for the test pattern sequence. Comparative analysis of the experimental results showed that even though the obtained designs lack in wiring uniformity they are promising in terms of overall performance criteria based on fault-coverage, test length, used area and dynamic power consumed.
Keywords :
automatic test pattern generation; built-in self test; cellular automata; computational complexity; electronic engineering computing; integrated circuit testing; BIST; NP-complete; built-in self-test; fault-coverage; low-power design topology; low-power test pattern generator design; nonuniform cellular automata model; polynomial-time algorithm; test pattern generation problem; test pattern sequence; Algorithm design and analysis; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Energy consumption; Hardware; Pattern analysis; Polynomials; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on
Print_ISBN :
0-7803-9060-1
Type :
conf
DOI :
10.1109/VDAT.2005.1500058
Filename :
1500058
Link To Document :
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