A TLM platform for system-on-chip simulation and verification

The complexity of system-on-chip (SOC) design is been making SOC simulation and verification being a big challenge for SOC designers (Rashinkar et al., 2001). To produce a high quality system in a short design cycle time, system simulation and verification must be done in an affordable time. An integrated environment from transaction level modeling (TLM) to HDL implementation with reusable verification strategy offers a potential solution. In this paper, the authors describe a TLM platform with mixed-language (SystemC/C++- and HDL) simulation capability and reusable verification features supplied to the member universities of the Canadian System-on-Chip Research Network (SOCRN) by Canadian Microelectronics Corporation (CMC). An example is used to illustrate the interface between high-level (SystemC/C++) model and low level (HDL) model for simulation in a mixed language environment.