All digital 625Mbps & 2.5Gbps deskew buffer design

Author

Lu, Hung-Wen ; Chang, Yin-Tin ; Su, Chau-Chin

Author_Institution

Dept. of Electr. Eng., National Central Univ., Chung-Li, Taiwan

fYear

2005

fDate

27-29 April 2005

Firstpage

263

Lastpage

266

Abstract

This paper describes an all digital 625Mbps and 2.5Gbps de-skew design for data recovery. It uses a confidence counter to serve as the loop filter that greatly reduces the circuit complexity and improves the jitter compression. The 625Mbps version has been implemented using TSMC 0.18μm 1P6M CMOS technology. Measurement results show that the phase resolution is 100ps and the de-skew range is 1.6ns. The output jitter is 48ps and the power consumption is 3.8 mW. For the 2.5Gbps version, the simulation results show that the timing resolution is 26ps, the total de-skew range is 400ps, the output jitter is 26.5ps, and the power consumption is 16 mW.

Keywords

CMOS integrated circuits; buffer circuits; high-speed integrated circuits; integrated circuit design; phase detectors; 0.18 micron; 16 mW; 2.5 Gbit/s; 3.8 mW; 625 Mbit/s; TSMC; all digital deskew buffer design; circuit complexity reduction; confidence counter; data recovery; jitter compression; loop filter; timing resolution; Bandwidth; Counting circuits; Delay lines; Detectors; Digital control; Jitter; Low pass filters; Phase detection; Phase locked loops; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on

Print_ISBN

0-7803-9060-1

Type

conf

DOI

10.1109/VDAT.2005.1500071

Filename

1500071