DocumentCode
1842777
Title
A multilevel sensing and program verifying scheme for Bi-NAND flash memories
Author
Chung, Chiu-Chiao ; Lin, Hongchin ; Shen, You-Min ; Lin, Yen-Tai
Author_Institution
Dept. of Electr. Eng., National Chung-Hsing Univ., Taichung, Taiwan
fYear
2005
fDate
27-29 April 2005
Firstpage
267
Lastpage
270
Abstract
A multi-level sensing and program verifying circuit is proposed for Bi-NAND type flash memories. The sensing circuit utilizes the advanced cross-coupled sense amplifier to achieve excellent immunity against mismatch effect, and reduce power consumption. The program-verifying scheme with dichotomous architecture simplifies the verifying circuit and speeds up verification process for multi-level cell arrays.
Keywords
NAND circuits; cellular arrays; circuit simulation; flash memories; semiconductor device models; sensor fusion; Bi-NAND flash memory; advanced cross coupled sense amplifier; cell arrays; mismatch effect immunity; multilevel sensing circuit; program verifying scheme; Acceleration; Circuits; Energy consumption; Flash memory; Image processing; Image storage; Operational amplifiers; Power amplifiers; Virtual manufacturing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on
Print_ISBN
0-7803-9060-1
Type
conf
DOI
10.1109/VDAT.2005.1500072
Filename
1500072
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