A low-power H.264/AVC decoder

Author

Lin, Ting-An ; Liu, Tsu-Ming ; Lee, Chen-Yi

Author_Institution

Dept. of Electron. Eng., National Chiao Tung Univ., Hsinchu, Taiwan

fYear

2005

fDate

27-29 April 2005

Firstpage

283

Lastpage

286

Abstract

In this paper, memory access could be saved in inter and intra prediction by adopting the proposed memory-efficient decoding ordering. In the proposed hierarchical syntax parser, gated clock technique could be effectively applied to reduce power. Simulation shows the proposed design consumes 88mW in real time decoding 1080HD video sequence.

Keywords

decoding; digital signal processing chips; hardware description languages; hardware-software codesign; integrated circuit design; logic circuits; low-power electronics; video codecs; 1080HD video sequence; 88 mW; H.264/AVC decoder; gated clock technique; hierarchical syntax parser; memory access; memory efficient decoding; real time decoding; Clocks; Decoding; Energy consumption; Entropy; MPEG standards; Registers; Standards development; Transform coding; Video coding; Video sequences;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on

Print_ISBN

0-7803-9060-1

Type

conf

DOI

10.1109/VDAT.2005.1500076

Filename

1500076

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1842871