A background comparator calibration technique for flash analog-to-digital converters

In modern integrated circuit systems, the flash ADC, which simultaneously compares input signal, is most suitable for high speed analog-to-digital conversion since it doesn´t require linear amplification. Due to the random input-referred offset voltage of the comparators, the linearity of the ADC transfer function is degraded. This offset is caused by device mismatches. And to overcome this inherent device´s constraint, several techniques have been proposed. This paper describes a background calibration technique that can perform offset trimming in comparators without interrupting the normal operation of the ADC. Since most of the required circuit overhead for the proposed scheme is in the digital domain and little modification is done to the analog critical signal path, the proposed scheme won´t degrade the speed of the circuit´s comparison function.