Jitter simulation and measurement of an all-digital clock generator with dynamic frequency counting loop

This paper presents a jitter simulation technique with Verilog hardware description language for an all-digital clock generator with dynamic frequency counting (DFC) loop. The Verilog simulation environment was selected for its high simulation speed, the direct relationship between the simulated and the built circuit. An all-digital clock generator has been fabricated in TSMC 0.35 mum 2P4M CMOS process to measure the jitter performance. The proposed jitter simulation with probabilistic distribution function has been successfully validated based on chip measurements.