DocumentCode
1843133
Title
Test structure data classification using a directed graph approach
Author
Cresswell, Michael W. ; Khera, Dheeraj ; Linholm, Loren W. ; Schuster, Constance E.
Author_Institution
Nat. Inst. of Stand. & Technol., Gaithersburg, MD, USA
fYear
1990
fDate
5-7 March 1990
Firstpage
193
Lastpage
198
Abstract
Directed graph techniques are introduced, serving as an expert system rule generator by classifying selections of tested wafers into groups based on similarities of the spatial distributions of their parametric test structure measurements. A self-normalizing equivalent vector inner product is devised to accommodate the ternary nature of the DC parametric test. It provides for test results that do not definitively pass a self-validation test. An algorithmic feature for avoiding special cases of nonoptimum search termination is conceived and implemented. The rules can be used to supplement those derived by other means of diagnostic process analysis, work-in-process wafer screening, and yield and reliability management.<>
Keywords
directed graphs; integrated circuit testing; semiconductor technology; DC parametric test; classifying selections of tested wafers; diagnostic process analysis; directed graph approach; expert system rule generator; parametric test structure measurements; reliability management; self-normalizing equivalent vector inner product; similarities spatial distributions; test structure data classification; wafer classification; work-in-process wafer screening; yield management; Classification tree analysis; Diagnostic expert systems; Electronic equipment testing; Expert systems; Fabrication; Integrated circuit testing; Joining processes; NIST; Semiconductor device testing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronic Test Structures, 1990. ICMTS 1990. Proceedings of the 1990 International Conference on
Conference_Location
San Diego, CA, USA
Type
conf
DOI
10.1109/ICMTS.1990.67902
Filename
67902
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