DocumentCode
1843159
Title
Instruction set architecture scheme for multiple fixed-width instruction sets and conditional execution
Author
Liang, Bor-Sung ; Wu, June-Yuh ; Lin, Jih-Yiing ; Ming-Chuan Huang ; Lai, ChiShaw ; Lien, Yun-Yin ; Chang, Ching-Hua ; Tsai, Pei-Lin ; Lin, Ching-Peng
Author_Institution
Sunplus Technol. Co., Ltd., Hsinchu, Taiwan
fYear
2005
fDate
27-29 April 2005
Firstpage
325
Lastpage
328
Abstract
An instruction set architecture scheme (ISA scheme) is proposed for multiple fixed-width instruction sets in embedded RISC processor. The ISA scheme can achieve efficient ISA change in instruction level. Besides, compared to current conditional execution methods, the parallel conditional execution (PCE) supported by ISA scheme has smaller code size and shorter execution cycle.
Keywords
embedded systems; instruction sets; microprocessor chips; reduced instruction set computing; ISA scheme; PCE; code size; conditional execution method; embedded RISC processor; execution cycle; instruction set architecture scheme; multiple fixed-width instruction sets; parallel conditional execution; Decoding; Instruction sets; Pipelines; Process design; Protocols; Reduced instruction set computing; Runtime; Switches; Technological innovation; Thumb;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on
Print_ISBN
0-7803-9060-1
Type
conf
DOI
10.1109/VDAT.2005.1500087
Filename
1500087
Link To Document