Title :
A global floorplanning technique for VLSI layout
Author :
Herrigel, A. ; Glaser, M. ; Fichtner, W.
Author_Institution :
Integrated Syst. Lab., Swiss Federal Inst. of Technol., Zurich, Switzerland
Abstract :
The floorplanning of rectangular cells is discussed. A new global approach that simultaneously accounts for different design goals is presented. A key aspect of this approach is a more general slicing structure representation of the floorplan that is not restricted to a special case of rectangular dissection and a two-dimensional partitioning procedure. A new model for the prediction of the associated shape functions is presented and an analytic optimization technique for the pin allocation is described
Keywords :
VLSI; circuit layout CAD; VLSI layout; associated shape functions; design goals; global floorplanning technique; optimization technique; pin allocation; rectangular cells; slicing structure representation; Circuits; Design optimization; Geometry; Laboratories; Power dissipation; Predictive models; Propagation delay; Shape; Very large scale integration; Wire;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location :
Cambridge, MA
Print_ISBN :
0-8186-1971-6
DOI :
10.1109/ICCD.1989.63335
