A programmable 25 MHz to 6 GHz rational-K/L frequency synthesizer with digital Kvco compensation

A programmable rational-K / L frequency multiplier that can synthesize any frequency between 25 MHz and 6 GHz from an input clock ranging from 1 GHz to 5.5 GHz is presented. The architecture employs a fractional-N input clock divider followed by a fractional-N PLL. In contrast to conventional architectures, it allows large K and L, whose maximum values are only limited by the word-length of digital SigmaDelta modulators. Additionally, to accommodate large Kvco variation, which is inevitable in wide tuning range VCOs, Kvco compensation is implemented without involving additional circuitry. This is an ideal solution to support a programmable serializer/deserializer on an FPGA.