Design and implementation of area-optimized AES based on FPGA

Author

Luo, Ai-Wen ; Yi, Qing-ming ; Shi, Min

Author_Institution

Coll. of Inf. Sci. & Technol., Jinan Univ., Guangzhou, China

Volume

1

fYear

2011

fDate

13-15 May 2011

Firstpage

743

Lastpage

746

Abstract

A new FPGA-based implementation scheme of the AES-128 (Advanced Encryption Standard, with 128-bit key) encryption algorithm is proposed in this paper. For maintaining the speed of encryption, the pipelining technology is applied and the mode of data transmission is modified in this design so that the chip size can be reduced. The 128-bit plaintext and the 128-bit initial key, as well as the 128-bit output of ciphertext, are all divided into four 32-bit consecutive units respectively controlled by the clock. The synthesis verification based on HJTC0.18um CMOS process shows that this new program can significantly decrease quantity of chip pins and effectively optimize the area of chip.

Keywords

CMOS integrated circuits; cryptography; field programmable gate arrays; integrated circuit design; logic design; microprocessor chips; pipeline processing; AES-128; CMOS process; FPGA; advanced encryption standard; area-optimized AES; chip pin; chip size; ciphertext; clock; data transmission; encryption algorithm; pipelining technology; size 0.18 mum; synthesis verification; word length 128 bit; Algorithm design and analysis; Clocks; Encryption; Field programmable gate arrays; Pipeline processing; Registers; Semiconductor device modeling; Area optimization; FPGA; Pipelining; Verilog;

fLanguage

English

Publisher

ieee

Conference_Titel

Business Management and Electronic Information (BMEI), 2011 International Conference on

Conference_Location

Guangzhou

Print_ISBN

978-1-61284-108-3

Type

conf

DOI

10.1109/ICBMEI.2011.5917042

Filename

5917042