Leakage power optimization for clock network using dual-Vth technology

Leakage power soars quickly as VLSI technology advance and supply voltage scaling, in the near future, it will exceed the dynamic power to become the main contributor of power dissipation. Previous methods on leakage power minimization always notice the negative effect of increasing the gate´s threshold voltage V_th and the power reduction is obtained based on power and speed (or performance) tradeoff. However, increasing the gate´s V_th could be used to adjust the subtrees´ imbalance for a clock tree. In this paper, for a gated clock tree, we analyze the bottom up merging segment generation process and conclude the conditions for increasing the gate´s V_th. Our idea is trying to assign high V_th to the gates without total wirelength and performance overheads, and in some cases, it could even be used to get more balanced subtrees. Experimental results on a set of ISCAS89 benchmark circuits demonstrate that our algorithm could assign more than half of the gates with high V_th, the resultant leakage power reduction is more than 43% without any total wirelength and delay penalties.