Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs

Author

Lu, J.-Q. ; Jindal, A. ; Kwon, Y. ; McMahon, J.J. ; Rasco, M. ; Augur, R. ; Cale, T.S. ; Gutmann, R.J.

Author_Institution

Focus Center-NY, Rensselaer Polytech. Inst., Troy, NY, USA

fYear

2003

fDate

2-4 June 2003

Firstpage

74

Lastpage

76

Abstract

Electrical and mechanical impacts of wafer bonding and thinning processes required for three-dimensional (3D) IC fabrication have been evaluated with interconnect structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional bonding and thinning process is used along with dielectric glue ashing to expose the previously tested interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer interconnect processing. Promising results on wafers with oxide interlevel dielectric (ILD) have been obtained, while some damages observed with the porous low-k ILD.

Keywords

copper; dielectric materials; integrated circuit interconnections; mechanical strength; porous materials; wafer bonding; wafer-scale integration; 3D IC fabrication; Cu; dielectric glue ashing; electrical impacts; inter-wafer interconnect processing; interconnect test structures; mechanical impacts; porous low-k oxide interlevel dielectrics; thinning processes; wafer bonding; Dielectrics; Fabrication; Glass; Inspection; Integrated circuit testing; Optical interconnections; Optical microscopy; Three-dimensional integrated circuits; Wafer bonding; Wet etching;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International

Print_ISBN

0-7803-7797-4

Type

conf

DOI

10.1109/IITC.2003.1219717

Filename

1219717