Title :
Backend process optimization for 90 nm high-density ASIC chips
Author :
Zarkesh-Ha, Payman ; Wright, Peter ; Lakshminarayanan, S. ; Cheng, C.-C. ; Loh, William ; Lynch, W.
Author_Institution :
Device Technol. Div., LSI Logic Corp., Milpitas, CA, USA
Abstract :
Based on the marketing, methodology, and manufacturing requirements of ASIC products, an optimum back-end process for high-density ASIC chips in a 90 nm technology is proposed. The chip size for high-density ASIC chips has stayed roughly constant between 7 and 14 mm on a side. High-density chips are achieved with tight pitch for all routing levels. Optimum performance is obtained with a thinner metal 2 and 3 Cu thickness of 0.25 versus 0.35 μm for the higher levels of metal.
Keywords :
application specific integrated circuits; integrated circuit interconnections; integrated circuit manufacture; 0.25 micron; 0.35 micron; 90 nm; Cu; Cu thickness; backend process optimization; high density ASIC chips; Application specific integrated circuits; Clocks; Cost function; Delay; Design optimization; Large scale integration; Logic devices; Manufacturing processes; Routing; Wiring;
Conference_Titel :
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
Print_ISBN :
0-7803-7797-4
DOI :
10.1109/IITC.2003.1219731
