A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 μm CMOS for 10mm on-chip interconnects

This paper presents a high speed and low energy transceiver for 10 mm long minimum width on-chip global interconnects. To improve the link bandwidth, the transmitter employs a capacitive-resistive pre-emphasis technique and the receiver employs the AC-coupled resistive feedback inverter (RFI) de-emphasis technique. Exploiting two emphasis techniques, the proposed interconnect achieves 1.26 GHz bandwidth which is 20 times improved compared to conventional link. As a result, it achieves error-free 3 Gb/s data rate and consumes less than 0.6 pJ/b during transmission by using low-swing and pulse signaling. The test chip is designed using 1.8 V 0.18 mum 6 M CMOS technology.