Title :
Efficient simulation of switch-level circuits in a hierarchical simulation environment
Author :
Wehbeh, Jalal A. ; Saab, Daniel G.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
Abstract :
Switch-level simulation provides a good level of abstraction for simulating digital MOS circuits. For handling large circuits, it is often necessary to represent parts of the circuit by high-level software models, in order to speed up the simulation process. This paper, considers hierarchical switch-level circuits, and investigates the use of extracted functional models at different levels in the hierarchy to increase the efficiency of simulation. A comparative study, on some sample circuits, is used to determine the ideal size of a module that should be simulated using its functional model
Keywords :
MOS integrated circuits; VLSI; digital simulation; integrated logic circuits; logic CAD; CAD; VLSI; digital MOS circuits; extracted functional models; hierarchical simulation environment; high-level software models; ideal size; logic circuits; switch-level circuits; Capacitance; Circuit simulation; Computational modeling; Computer simulation; Discrete event simulation; Logic circuits; Resistors; Switches; Switching circuits; Very large scale integration;
Conference_Titel :
VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on
Conference_Location :
Notre Dame, IN
Print_ISBN :
0-8186-5610-7
DOI :
10.1109/GLSV.1994.289963
