Low-power differential CML and ECL BiCMOS circuit techniques

Author

Sharaf, K.M. ; Elmasry, M.I.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

fYear

1994

fDate

4-5 Mar 1994

Firstpage

208

Lastpage

213

Abstract

The performance of the different two-level series-gated CML BiCMOS schemes has been studied and compared. Simulation results, based on a 0.6-um BiCMOS technology, have shown an improvement of 42% in the maximum frequency of operation of the BJT-MOS static frequency divider over the BJT scheme operating an the low power regime (<1 mW). Moreover, the BJT-MOS frequency divider configuration exhibits a high input sensitivity throughout the frequency range of operation. A new BiCMOS Active-Pull-Down (APD) ECL circuit is also presented which can achieve 32% improvement in the load driving capability and 43% improvement in the propagation delay over conventional ECL circuit

Keywords

BiCMOS integrated circuits; emitter-coupled logic; frequency dividers; integrated logic circuits; 0.6 micron; 1 mW; BJT-MOS static frequency divider; BiCMOS circuit techniques; active-pull-down ECL circuit; low-power differential type; propagation delay; series-gated CML; BiCMOS integrated circuits; Circuit simulation; Computational modeling; Energy consumption; Frequency conversion; Frequency synthesizers; MOS devices; Mobile communication; Power dissipation; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on

Conference_Location

Notre Dame, IN

Print_ISBN

0-8186-5610-7

Type

conf

DOI

10.1109/GLSV.1994.289967

Filename

289967