Numerical modeling and characterization of the stress migration behaviour upon various 90 nanometer Cu/Low k interconnects

Author

Huang, T.C. ; Yao, C.H. ; Wan, W.K. ; Hsia, Chin C. ; Liang, M.S.

Author_Institution

Adv. Module Technol. Div., Taiwan Semicond. Manuf. Co., Ltd., Hsin-Chu, Taiwan

fYear

2003

fDate

2-4 June 2003

Firstpage

207

Lastpage

209

Abstract

Stress migration (SM) behavior found on various Cu/Low k interconnects is analyzed in this article. The simulation results demonstrate that the minimum stresses always occur on/near via bottom, which makes the dummy via insertion an effect way relieving SM induced circuit failure. A numerical index reflecting the bulk vacancy density evolution is developed from the simulated stress distribution and aimed at predicting the destination of the migrating vacancies driven by the thermally generated stress gradient of the interconnect system. Though still in its burgeoning stage, the simulated SM behavior using the index compared well against those experimentally collected data.

Keywords

copper; dielectric materials; failure analysis; finite element analysis; integrated circuit interconnections; integrated circuit modelling; thermal stresses; vacancies (crystal); 90 nm; Cu; bulk vacancy density; burgeoning stage; nanometer Cu/Low k interconnects; numerical modeling; stress migration circuit failure; thermally generated stress gradient; Circuit simulation; Circuit synthesis; Circuit testing; Copper; Finite element methods; Integrated circuit interconnections; Numerical models; Samarium; Thermal resistance; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International

Print_ISBN

0-7803-7797-4

Type

conf

DOI

10.1109/IITC.2003.1219755

Filename

1219755