VLSI implementation of CORDIC angle units

Author

Lee, Jeong-A ; Ahmad, Mubashir

Author_Institution

Dept. of Electr. Eng., Houston Univ., TX, USA

fYear

1994

fDate

4-5 Mar 1994

Firstpage

144

Lastpage

149

Abstract

We design angle units using Lager tools both by a conventional CORDIC algorithm and a fast algorithm called Constant-Factor Redundant CORDIC (CFR-CORDIC) and show that the CFR-CORDIC occupies more than twice the area of a conventional CORDIC but offers good speed-up. We discuss VLSI design issues using Lager such as system partitioning and grouping, floor planning, width and height manipulation to obtain the smallest geometry, and the limitation of the standard cell design approach. In addition, a bit encoding scheme of a signed digit number representation, which simplifies the implementation of the negation is presented

Keywords

VLSI; circuit layout CAD; digital arithmetic; digital signal processing chips; parallel architectures; CAD program; CORDIC angle units; Lager tools; VLSI design; VLSI implementation; bit encoding scheme; constant-factor redundant CORDIC; floor planning; height manipulation; high level design; negation implementation; parallel architecture; signed digit number representation; system grouping; system partitioning; width manipulation; Algorithm design and analysis; Application software; Concurrent computing; Difference equations; Encoding; Geometry; Partitioning algorithms; Signal processing; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on

Conference_Location

Notre Dame, IN

Print_ISBN

0-8186-5610-7

Type

conf

DOI

10.1109/GLSV.1994.289979

Filename

289979