Cu interconnects and low-k dielectrics, challenges for chip interconnections and packaging

The continuing scaling trend in microelectronic circuit technology has a significant impact on the different IC interconnection and packaging technologies, mainly due to the increasing pad densities and the use of novel materials. This results in particular challenges for the chip connection technology (wire bonding & flip chip) as well as the package technology. Some of these problems may be resolved through the use of additional metal and dielectric layers, processed on top of the IC passivation, e.g. to redistribute chip pin-out into a regular array. Such wafer-level packaging techniques may result in significant cost savings in device packaging. They do however also provide new opportunities for the circuit design. These additional layers may e.g. be used for low loss, high speed on chip interconnects, clock distribution circuits, efficient power/ground distribution and to realize high Q inductors on chip.