A general circuit topology of multilevel inverter

A generalized circuit topology of multilevel voltage source inverters which is based on a direct extension of the three-level inverter to higher level is proposed. The circuit topologies up to five-level are presented. The proposed multilevel inverter can realize any multilevel pulsewidth modulation (PWM) scheme which leads to harmonic reduction and provides full utilization of semiconductor devices like GTOs, especially in the high power range where high voltage can be applied. The capacitor voltage balancing problem is discussed and a circuit remedy for such a problem is given