Title :
Reliability improvement of 9 nm-node Cu/low-k interconnects
Author :
Matsumoto, S. ; Ishii, A. ; Tomita, K. ; Hashimoto, K. ; Nishioka, Y. ; Sekiguchi, M. ; Iwasaki, Akira ; Isono, S. ; Satake, T. ; Okazaki, G. ; Fujisawa, M. ; Matsumoto, M. ; Yamamoto, S. ; Matsuura, M.
Author_Institution :
Semicond. Co., Matsushita Electr. Ind. Co., Ltd., Japan
Abstract :
We have studied electromigration (EM) and stress-induced voiding (SV) behaviors based on our 90 nm-node Cu/low-k interconnect processes, and demonstrated successful improvement of the interconnect reliability. In EM study wide bimodal failure distribution was found only in the particular EM test structure. We identified that it caused by the lack of wettability between Cu and the barrier metal in the vias, and demonstrated that the optimization of the barrier metal thickness could suppress it. In SV behavior, we revealed a mechanism of the voiding under the vias that was due to the initial existence of the nuclei of the void before high temperature storage test. The failure mode was suppressed by optimizing preheat temperature of M2 barrier metal deposition.
Keywords :
copper; dielectric materials; dielectric thin films; electromigration; failure analysis; heat treatment; integrated circuit interconnections; internal stresses; silicon compounds; tantalum; voids (solid); 90 nm; Cu-Ta; Cu/low k interconnects reliability; SiO2-SiC; SiOC-SiO2; barrier metal deposition; barrier metal optimization; bimodal failure distribution; electromigration; heat treatment; high temperature storage test; stress induced voiding; wettability; Atherosclerosis; Dielectrics; Failure analysis; Lithography; Reliability engineering; Semiconductor device reliability; Silicon carbide; Temperature; Testing; Ultra large scale integration;
Conference_Titel :
Interconnect Technology Conference, 2003. Proceedings of the IEEE 2003 International
Print_ISBN :
0-7803-7797-4
DOI :
10.1109/IITC.2003.1219771