The design of a fault tolerant GEQRNS processing element for linear systolic array DSP applications

Author

Smith, Jeremy C. ; Taylor, Fred J.

Author_Institution

Dept. of Electr. Eng., Florida Univ., Gainesville, FL, USA

fYear

1994

fDate

4-5 Mar 1994

Firstpage

46

Lastpage

49

Abstract

In this work the design of a Galois Enhanced Quadratic Residue Number System processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been, optimized to perform multiply-accumulate type operations on complex operands. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which occur during operation. A prototype integrated circuit has been fabricated in 1.5 μm CMOS technology, which is shown to operate at 40 MHz

Keywords

CMOS integrated circuits; VLSI; digital arithmetic; digital signal processing chips; fault tolerant computing; systolic arrays; 1.5 micron; 40 MHz; CMOS technology; DSP applications; GEQRNS processing element; Galois Enhanced Quadratic Residue Number System; complex operands; fault tolerant element; linear systolic array; multiply-accumulate type operations; processor architecture; prototype integrated circuit; Arithmetic; Bandwidth; CMOS process; CMOS technology; Digital signal processing; Equations; Fault tolerance; Petroleum; Signal processing; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on

Conference_Location

Notre Dame, IN

Print_ISBN

0-8186-5610-7

Type

conf

DOI

10.1109/GLSV.1994.289997

Filename

289997