Design of low power, high density gallium arsenide asynchronous primitives for multimedia computing

The present trend to use VLSI DSP for multimedia computing and communications imposes new, very high level of performance requirements for the underlying technology. The concept of personal interactive mobile multimedia communicator (M/sup 3/C) requires very high performance in terms of processing speed and the associated power-area product. Portability of the system imposes further complexity in terms of the need for low voltage operation. This paper presents the design methodology for highly pipelined, asynchronous primitives suitable for multimedia applications using gallium arsenide MESFET, as the base technology implementation of latched logic design style (PDLL, LCFL). The use of latched logic together with the absence of the global clock provides for low power dissipation while maintaining the very high speed of the system. The application of the modified ring notation to layout the pipelined system allows circuit densities in excess of 10000 active devices per mm/sup 2/ in 0.6 /spl mu/m GaAs MESFET technology and operating at less than 1 volt power supply.