GaAs multiplier and adder designs for high-speed DSP applications

This paper describes two designs in 0.6 /spl mu/m gallium arsenide MESFET technology of arithmetic primitives widely used in high-speed DSP integrated circuits. Two designs are: 16/spl times/16-bit multiplier with a simulated delay of 2.4 ns, and a 32-bit adder with a measured delay of 1.3 ns. These speeds were achieved at with a 0.9 V power supply and the delays quoted are non-pipelined so that the latency is 1. The power dissipation for both designs was found to be less than 0.5 /spl mu/W/gate/MHz. Both designs use a layout technique called "Modified Ring Notation" that improves the packing density of these chips compared to previous designs using the Ring Notation. The paper presents the issues raised in the architecture designs such as minimising the wire lengths, compacting the cell layouts, sizing the transistors, and introducing buffers to minimise the fan-out loading on the critical path.