Floorplanning for mixed macro block and standard cell designs

Author

Shanbhag, Arun ; Danda, SrinivasaRao ; Sherwani, Naveed

Author_Institution

Dept. of Comput. Sci., Western Michigan Univ., Kalamazoo, MI, USA

fYear

1994

fDate

4-5 Mar 1994

Firstpage

26

Lastpage

29

Abstract

In this paper, we present ARCHITECT, the floorplanner for high performance Mixed Block and Cell designs. A novel and significant feature of ARCHITECT is that it exploits the flexibility of the standard cell regions by generating arbitrary rectilinear shapes for the flexible blocks. We have implemented ARCHITECT on a Sun SPARC station 1+ using C and Xview. We have tested the floorplanner on various randomly generated examples. Experimental results indicate that ARCHITECT generates floorplans with minimal white space within the user specified bounds

Keywords

VLSI; circuit layout CAD; logic CAD; logic arrays; ARCHITECT; C; Sun SPARC station 1+; VLSI design; Xview; arbitrary rectilinear shapes; floorplanner; initial placement; irregular rectilinear boundary block assignment; minimal white space; mixed macro block design; randomly generated examples; standard cell designs; Algorithm design and analysis; Chip scale packaging; Circuit optimization; Computer science; Scholarships; Shape control; Sun; Testing; Very large scale integration; White spaces;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on

Conference_Location

Notre Dame, IN

Print_ISBN

0-8186-5610-7

Type

conf

DOI

10.1109/GLSV.1994.290001

Filename

290001