High-voltage compliant, capacitive-load invariant neural stimulation electronics compatible with standard bulk-CMOS integration

A neural stimulator architecture is described which can drive biphasic, constant-current waveforms through a wide range of electrode impedances with approximately ±11V compliance, while using a low-voltage, modern bulk-CMOS technology. The design, based on an H-bridge topology, utilizes a regulated “discharge” phase during biphasic delivery to account for “capacitive-looking” electrodes, extending the bipolar on-chip headroom of a CMOS stimulator. Stimulus current is supplied by integrated switched-capacitor, dynamic voltage supplies (0-12V), which operate with closed-loop control. The stimulator topology also uses a single, low-voltage current DAC to regulate the entire biphasic current waveform. The voltage supply block has been fabricated in 65nm standard CMOS. Cadence simulations of the proposed biphasic driver, designed for 250μA maximum current, are given for several “high” impedance electrode models. The efficacy of the proposed integrated electronics in potential neural stimulation applications is demonstrated with a board-level prototype, which has been designed and evaluated in-vivo (rat).