Automated system partitioning for synthesis of multi-chip modules

We present a system-level partitioning technique for the synthesis of multi-chip modules. It is based on the stochastic evolution heuristic, which is an effective heuristic for solving several combinatorial optimization problems. We perform the partitioning at the behavioral level. The advantage of partitioning at the behavioral level is that both area and time constraints can be taken care of at the system level and also that scheduling/allocation can be applied concurrently to system-level partitioning. We formulate the partitioning problem as an extension to the network-bisectioning problem for which the stochastic evolution heuristic has been shown to provide better results than the simulated annealing technique. Preliminary scheduling/allocation and pin sharing are also performed simultaneously to estimate the area and pincount of each of the partitions. Efficient partitions are obtained for some of the digital signal processing applications in reasonable CPU time