Title :
Integration Of Clock Skew And Register Delays Into A Retiming Algorithm
Author :
Soyata, Tolga ; Friedman, Eby G.
Author_Institution :
University of Rochester
Keywords :
Circuit synthesis; Clocks; Combinational circuits; Delay estimation; Frequency estimation; Frequency synchronization; Latches; Pipeline processing; Pulse circuits; Registers;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
IEEE
Print_ISBN :
0-7803-1281-3
