A parallel low-complexity coefficient computation processor for the MMSE-DFE

Author

Al-Dhahir, Naofal ; Sayed, Ali H.

Author_Institution

Corporate R&D Center, Gen. Electr. Co., Niskayuna, NY, USA

Volume

2

fYear

1997

fDate

2-5 Nov. 1997

Firstpage

1586

Abstract

A modular parallel architecture for a MMSE-DFE coefficient computation processor is presented. The architecture is based on the QR factorization of a channel-and-noise-dependent data matrix and is implemented using CORDIC processors within a systolic array architecture. Implementation issues including the number of CORDIC stages and the bit precision required in a fixed-point implementation are investigated through computer simulations.

Keywords

computational complexity; decision feedback equalisers; digital arithmetic; digital signal processing chips; least mean squares methods; matrix decomposition; systolic arrays; CORDIC processors; CORDIC stages; MMSE-DFE; QR factorization; bit precision; channel-and-noise-dependent data matrix; fixed-point implementation; implementation issues; modular parallel architecture; parallel low-complexity coefficient computation processor; systolic array architecture; Autocorrelation; Computer architecture; Computer simulation; Concurrent computing; Decision feedback equalizers; Delay; Electronic mail; Finite impulse response filter; Parallel architectures; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Systems & Computers, 1997. Conference Record of the Thirty-First Asilomar Conference on

Conference_Location

Pacific Grove, CA, USA

ISSN

1058-6393

Print_ISBN

0-8186-8316-3

Type

conf

DOI

10.1109/ACSSC.1997.679170

Filename

679170