A high SFDR direct digital synthesizer with frequency error free output

In this paper, an error-compensation method is proposed to achieve high spurious free dynamic range (SFDR) in direct digital synthesizers (DDS) design. This method allows very small ROM storage, while leaving the resultant errors corrected by the error-compensation circuits. An extended phase accumulator (EPA) is also adopted to provide arbitrary output frequency, thus can achieve frequency error free output. Experimental results show that the DDS using only 256 bits of ROM can achieve 104 dBc SFDR for output signal at 20 MHz with a clock frequency of 100 MHz. The effect of EPA is also demonstrated in the design.