A novel memory architecture for multicore SDR systems

For conventional wireless transceiver architectures with software-defined radio (SDR) technology, the communication between microcontrollers, DSPs (digital signal processors), and memories are through public shared buses. As wireless standards change frequently, the demands of bus bandwidth increase. To avoid bus bottlenecks and to get better performance, the wireless transceiver architectures with concatenate memories and concatenate buses are proposed. The application-specific instruction-set processor (ASIP) for the IEEE 802.11p standard and the electronic system-level (ESL) virtual platform for the inner receiver of IEEE 802.11p are built. Via the proposed transceiver architectures with concatenate memories and concatenate buses, the bandwidth of communication between DSPs through public shared buses can be saved because the communications between DSPs and concatenate memories are through concatenate buses.